In recent years, in the field of electronic devices, there have been demands for a furthermore compact and higher performance capacitor element as an essential circuit element in a variety of electronic circuits along with electronic circuits becoming higher in density and more highly integrated.
For example, a thin film capacitor using a single-layer dielectric thin film is behind in making a compact integrated circuit with a transistor or other active element, which has bean a factor of hindering realization of an ultra-high integrated circuit. It was a low permittivity of a dielectric material to be used that has hindered attaining of a compact thin film capacitor. Accordingly, it is significant to use a dielectric material having a high permittivity to realize a more compact thin film capacitor with a high capacitance.
Also, in recent years, a conventional multilayer film of SiO2 and Si3N4 has become hard to respond to a capacitor element for a DRAM of the next generation (gigabit generation) in terms of capacitance density, and a material system having a higher permittivity has gathered attention. In such a material system, an application of TaOx (ε=30 or smaller) has been mainly studied but development of other materials comes to be actively pursued.
On the other hand, as a dielectric material having a relatively high permittivity, (Ba, Sr)TiO3 (BST) and Pb(Mg1/3Nb2/3)O3 (PMN) are known.
It can be considered that it is possible to attain a compact body when a thin film capacitance element is composed of a dielectric material of this kind.
However, when using dielectric materials of this kind, the permittivity declined as the dielectric film became thinner in some cases. Also, a leakage property and a breakdown voltage were deteriorated due to apertures generated on the dielectric film as the film became thinner in some cases. Furthermore, the dielectric film to be formed had poor surface smoothness and, moreover, it was liable that the change rate of permittivity against temperature declined. Note that due to a large effect by lead compounds, such as PMN, on the environment, a high capacitance capacitor not containing lead has bean desired.
On the other hand, to realize a more compact multilayer ceramic capacitor with a larger capacitance, it is desired that a thickness of one dielectric layer is made as thin as possible (a thinner layer) and the number of dielectric layers at a predetermined size is increased as much as possible (an increase of stacked layers).
A multilayer ceramic capacitor is produced by a sheet method or printing method. The sheet method is a method of forming a dielectric green sheet layer on a carrier film by using a dielectric layer paste by the doctor blade method, etc., printing an internal electrode layer paste to be a predetermined pattern thereon, then, releasing them one by one and stacking the same. The printing method is a method of alternately printing a dielectric layer paste and an internal electrode layer paste for a plurality of times on a carrier film, for example, by using the screen printing method, then, removing the carrier film. However, for example, when producing a multilayer ceramic capacitor by the sheet method, the dielectric layer could not be made thinner than ceramic material powder. Furthermore, it was difficult to make the dielectric layer thin, for example, as 2 μm or thinner because of problems of short-circuiting and breaking of internal electrode, etc. due to a defective dielectric layer. Also, when a thickness of one dielectric layer was made thinner, the number of stacked layers was also limited. Note that the same problem remained in the case of producing a multilayer ceramic capacitor by the printing method.
Due to the above reasons, there was a limit in making the multilayer ceramic capacitor more compact and higher in capacitance. Thus, a variety of proposals have been made to solve the problem (for example, the patent article 1: the Japanese Patent Publication No. 2000-124056, the patent article 2: the Japanese Patent Publication No. 11-214245, the patent article 3: the Japanese Patent Publication No. 56-144523, the patent article 4: the Japanese Patent Publication No. 5-335173 and the patent article 5: the Japanese Patent Publication No. 5-335174, etc.).
In these publications, methods of producing a multilayer ceramic capacitor formed by alternately stacking dielectric thin films and electrode thin films by using a variety of thin film forming method, such as the CVD method, evaporation method and sputtering method are disclosed.
However, a dielectric thin film formed by the methods described in the publications had poor surface smoothness, and short-circuiting of electrodes arose when stacking too much, so that those having 12 or 13 stacked layers or so were able to be produced at most. Therefore, even when the capacitor could be made compact, a higher capacitance could not be attained.
Note that as described in the non-patent article 1 [“Particle Orientation of Ferroelectric Ceramic having Bismuth Layer Structure and Application Thereof to Piezoelectric and Pyroelectric Material” by Tadashi Takenaka, pp. 23 to 77 in chapter 3 of Kyoto University Doctor of Engineering Thesis (1984)], it is known that a bulk bismuth layer compound dielectric obtained by the sintering method is composed of a composition expressed by the composition formula of (Bi2O2)2+(Am−1BmO3m+1)2− or Bi2Am−1BmO3m+3, wherein “m” is a positive number from 1 to 8, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta, Sb, V, Mo and W.
However, in this article, nothing was disclosed on under what condition (for example, a relationship of a substrate surface and a c-axis orientation degree of a compound) when making the composition expressed by the above composition formula thinner (for example 1 μm or thinner), a thin film capable of giving a relatively high permittivity and a low loss, having an excellent leakage property, improved breakdown voltage, excellent temperature characteristics of permittivity, and excellent surface smoothness could be obtained.
The present inventors have developed a thin film capacitance element composition disclosed in the patent article 6 (PCT/JP02/08574) and filed before. As a result of carrying on further experiments, they found that the c-axis orientation degree of the compound can be still improved by making Bi contained in excess of a stoichiometric composition of the bismuth layer compound, and completed the present invention.
Note that a thin film composed of the thin film capacitance element composition described in the patent article 6 can be formed by a variety of thin film forming methods, such as the CVD method, evaporation method and sputtering method. But particularly when forming by a solution method (the sol-gel method and MOD (Metal-Organic Deposition) method), the c-axis orientation degree was hard to be improved. It was because firing for crystallization was performed after forming a coating film to be a certain film thickness on a substrate, so that it was easily affected by the substrate and the c-axis orientation was hard to be improved regardless of the direction of the orientation of the substrate.
Also, the non-patent article 2 [2001 Journal of Applied Physics Vol. 40 (2001) pp. 2977 to 2982, Part 1, No. 4B, April 2001] reports that the c-axis orientation degree can be improved by adding Bi excessively in a dielectric thin film of (Bi,La)4Ti3O12. However, this article only discloses a bismuth layer compound expressed by a composition formula (Bi2O2)2+(Am−1BmO3m+1)2− or Bi2Am−1BmO3m+3, wherein “m” is an odd number. Also, in this article, the excessive adding quantity of Bi is low as 2.5 to 7.5 mol % (0.4 mol or less with respect to the stoichiometric composition), which was proved to be insufficient to improve the leakage current resistance characteristic according to an experiment by the present inventors.